Research Projects | Future Architecture and System Technology for Scalable Computing

research

Compute Express Link (CXL)

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CXL is an open-standard high-speed interconnect technology that enables data transfer between CPUs, SmartNICs, GPUs, and other devices. It offers three protocols—CXL.io, CXL.cache and CXL.memory—to balance I/O, coherent caching and direct memory access.

Intra- and Inter-host Network System and Host Microarchitecture Resource Management

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Host servers have undergone a substantial increase in complexity, and cloud deployments now routinely host multiple applications and tenants on the same physical hardware. This convergence makes efficient orchestration of shared resources and low-latency intra-host communication essential for maintaining peak system performance and efficiency. Our research addresses these challenges through dynamic workload balancing across CPU cores and accelerators (e.g., SmartNICs), leveraging self-developed programmable PCIe switch for RDMA performance isolation and communication efficiency improvement, and fine-grained management of host shared resources (e.g., LLC) and microarchitectural features (e.g., Direct Cache Access). Our solutions significantly reduce tail latency, boost throughput for latency-sensitive network applications, and enhance overall system efficiency.

On-Chip Accelerators

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Intel has integrated diverse on-chip accelerators into its recent flagship datacenter CPU products. Our group has conducted in-depth investigations four of these cutting-edge accelerators, Data Streaming Accelerator (DSA), Dynamic Load Balancer (DLB), In-memory Analytics Accelerator (IAA), and QuickAssist Technology (QAT). We are the first research group to offer comprehensive guidelines, practical use cases, and distinctive enhancements to maximize the effectiveness and performance of these accelerators.

LLM System

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The deployment of Large Language Models (LLMs) poses significant challenges on cost and design complexity, as training and serving LLMs demand vast computational throughput and enormous memory capacity. Our group conducted research on identifying performance bottlenecks for LLM workloads, integrating heterogeneous hardware components including CPUs, GPUs, FPGAs, and CXL devices into design, targeting on cost-efficient and high-performance LLM systems.

Processing In / Near Memory (PIM/PNM)

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Compute-in-Memory (PIM) tackles the “memory wall” by moving simple compute units directly into DRAM, overcoming physical limits on off-chip bandwidth (PCB traces, package pins, thermal caps) and slashing data-movement energy. Samsung’s Aquabolt-XL is the first commercially fabricated HBM2-PIM device. It embeds a 16-lane FP16 SIMD array plus lightweight control and register files at each bank boundary of a standard eight-die HBM2 stack (16 pseudo-channels total), preserving JEDEC timing and drop-in form factor.